As integrated circuit (IC) features continue to be scaled down to deep submicrometer (μm) dimensions (0.05-0.20 μm), metal interconnects become a bottleneck for continued IC performance improvement. Within a typical interconnect structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered interconnect schemes, such as, for example, dual damascene wiring structures based on copper. Copper based interconnect structures are desirable over previously used aluminum interconnects due to their efficacy in providing high speed signal transmission between large numbers of transistors on a complex semiconductor chip.
Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) can be achieved by embedding the metal lines and vias in a low-k dielectric material having a dielectric constant of approximately 3.9 or less, or in an ultra low-k (ULK) dielectric material having a dielectric constant of approximately 3.0 or less. One method for forming vertical and horizontal interconnects is by using damascene or dual damascene method. In the damascene method, one or more dielectric materials, including low-k dielectric materials, are deposited and pattern etched to form vias and lines. Conductive materials such as copper and barrier layer materials used to prevent diffusion of copper into the surrounding low-k dielectric material are then inlaid into the etched pattern. Any excess copper and barrier layer materials external to the etched pattern remaining on the field of the substrate are then removed.
However, reliability problems are associated with these structures. During integration, reliability stress, or extended use, a chip interconnect structure made in a low-k dielectric material may fail or degrade due to poor adhesion, moisture uptake, and various stress migration between the metal liner/metal and the low-k dielectric material. These reliability issues result from defects in the porous low-k dielectric material and the metal liner/metal of the interconnects, which results in oxidizing species such as H2O or O2 interacting with the metal. The varying compositions and material properties of the various deposition layers used in conventional hardmasks (oxide adhesion layer, transitional layer, low-k/UK dielectric layer, and layers of oxygen-containing organosilicon compounds) make it difficult to form defect free lines and vias. During the etching process, the various hardmask layers react differently to the etchants, resulting in interconnects that have a rough or uneven profile (e.g., undercut profile) that negatively affects performance. In addition to these integration problems, conventional processes used to form hardmasks involve multiple tool sets and several steps in which the process conditions must be altered.
Accordingly, it may be desirable to overcome the deficiencies and limitations described hereinabove.